Related Work Experience

8/2005 to Date

Assistant (9/2005 – 8/2011) and Associate (8/2011 to date) Professor, Department of Computer Science, Texas State University, San Marcos, Texas

Conducting research on data compression and pattern recognition, complex fuzzy logic, and effort based usability evaluation. Additional research areas includes signal processing and combinatorial optimization.

Teaching graduate and undergraduate courses in multimedia programming, data communications, computer architecture, computer graphics, formal languages, and graphical user interface.

Supervising research and individual study courses with graduate and undergraduate students; Seven students are/were pursuing their master's projects under my supervision.

Serving on several university and departmental committees, and as a reviewer for several journals and conferences. Additionally, I have served as the program chair for two conferences.

Published over 50 refereed journal, conference, and workshop papers and secured (as a PI, Co-PI, or collaborator) over $500,000 in funded research.


7/96 – 8/2005 Worked for Motorola / Freescale in three main locations / positions:

8/2002 – 8/2005

Architecture Manager, DSP Platforms, Motorola / Freescale Semiconductor , Austin, Texas

Managed a team of computer architects and DSP application engineers. The main task of the Freescale team was to drive the DSP technology to support data communication, multimedia, and data compression applications and standards.

Led the definition of Motorola’s next-generation high-performance DSP architecture and worked along with StarCore LLC to define the SC140e, SC2400, and SC3400. Made several important contributions to the architecture, micro-architecture, and echo-system of the DSP, including specification of DSP instruction set architecture (ISA) for the support of communication and video compression applications, enhancement of compiled code performance, definition of advanced micro-architecture features, development of simulation tools, and verification of the compatibility model to legacy code.

Participated in the design of the Signal Processing Enhancement unit of the embedded PowerPC architecture concentrating on enhancements related to video compression and image processing.

Conducted analysis of StarCore performance as a Single Core Modem (SCM) for 2.5G, 2.75, and 3G communication protocols. The recommendations of this study were used to design the Freescale SCM system architecture.


8/99 – 8/2002

Applications Manager, DSP Platforms, NCSG, Motorola Semiconductor, Work location - StarCore a joint R&D center with Lucent / Agere, Atlanta, Georgia

Managed a team of DSP application engineers. Used DSP application domain knowledge to impact the ISA of next generation DSP in order to efficiently support data communication, multimedia, and data compression applications.

Made several important contributions to the architecture, micro-architecture, and echo-system of the DSP, including specification of DSP ISA, enhancement of compiled code performance, and verification of the compatibility model to legacy code.

Developed code for benchmarks, and made customer presentations.


6/96 - 7/99

Section Manager, Motorola Semiconductor, Israel

Developed DSP ISA for a proprietary single instruction multiple data (SIMD) parallel architecture (code name Olive).

Developed motion estimation algorithms for video compression and real-time MPEG2 video encoding and pre-processing reference design on a system based on Olive.

Developed the code compression schema, used in Motorola automotive controllers.

Assumed responsibility for establishing relations with universities including coordination of activities such as mutual research, student projects, student assistantships, and awards for excellent students. In addition, this activity included teaching undergraduate courses, mainly in digital signal processing, supervising student projects, and establishing an Onyx based DSP laboratory in Ben-Gurion University. Motorola SPS funded $80K toward the Lab and the authoring of a book on the SC140.


9/89 to 5/96

Assistant (9/89 - 4/95) and Associate (4/95 - 5/96) Professor of Computer Science, Florida Institute of Technology, Melbourne, FL, 32901.

Conducted research in computer vision, data compression, and pattern recognition. Taught graduate and undergraduate courses in artificial intelligence, image processing, pattern recognition, computer architecture, data communications, and Java.

Supervised, research, senior projects, and Master thesis of 19 graduate students, as well as one Ph.D. dissertation. Published over twenty refereed journal and conference papers and secured (as a PI or Co-PI) over $180,000 in funded research.

Initiated a program for distance learning, started one of the first courses in the nation in Java, and was very active in interacting and collaborating with students and peers at all levels. Assumed responsibility for overseeing the computing resources and computer labs of the department and was able to find innovative ways to get new equipment despite low budget. Served as a member of the Florida Artificial Intelligence Research Symposium committee. Reviewed papers, assisted in organizing the annual meetings, set the subjects for special sessions, and chaired FLAIRS-95.

Served as a reviewer for the IEEE Software.


7/83 - 6/86

Software Engineer, Tadiran LTD, Communication Division, Digital Equipment Plant, Applied research Department, Holon, Israel

Developed algorithms for speech compression, speech recognition, image coding, and data encryption.


2/82 - 7/83

Software Engineer, Ben-Gurion University, Department of Electrical Engineering, Beer-Sheva, Israel.

Developed software for speaker verification, dynamic time warping, clustering, and classification.