I'm a first-year Ph.D. student in the Department of Computer Science at Texas State University, where I was previously an adjunct lecturer teaching computer architecture, digital logic, and CS 2. I have an M.S. in computer science from Texas State, a B.S. in electrical and computer engineering and engineering and public policy from Carnegie Mellon University, and in between the two degrees I was a senior design engineer at ARM Austin, where I designed the unit-level verification environment for the load/store unit and L1 data cache of an out-of-order, cache coherent multicore processor.
I'm advised by Dr. Apan Qasem in the Compilers Research Lab (CRL), working on techniques to improve the performance and programmability of heterogeneous memory architectures. More broadly, I have research interests in computer architecture, performance optimization, and in strategies that span the intersection of architecture with compilers, programming languages, and algorithms to improve GPGPU and heterogeneous programmability. As a masters student, I was a research assistant in Dr. Martin Burtscher's Efficient Computing Laboratory (ECL), where I worked on software and microarchitectural techniques to efficiently accelerate irregular codes on GPUs. I was fortunate to have this work supported by a 2011 NSF Graduate Research Fellowship.
I'm also interested in computer science education and in pedagogical and curricular practices to connect more diverse students to computer science and engineering, and I'm particularly passionate about increasing the participation and retention of young women in my field.